1. Field of the Invention
The present invention relates to a clock switching circuit for dynamically switching a plurality of clocks.
2. Related Background Art
A clock switching circuit according to a second embodiment in Unexamined Japanese Patent Publication No. 2001-332961 is conventionally present as a circuit wherein no hazard accompanies an output clock signal when a plurality of clocks are switched. According to this conventional example, the technique disclosed is intended to prevent the occurrence of a hazard in the output when a plurality of clock signals are switched.
However, two types of clock signals can not be switched in the circuit disclosed in this publication unless these signals interact with each other. Thus, when this circuit is employed to cope with the switching of an increased number of clocks, such as three or four types, all the clocks must be repeatedly and simultaneously supplied to the circuit, and this constitutes a barrier that forestalls a reduction in the power consumption.